1. Field of the Invention
This invention relates to the analysis of defects detected in integrated circuit (IC) devices, and more particularly to the encoding of test results for multiple IC devices into a serial digital data bitstream for digital signal processing (DSP) analysis.
2. Description of the Related Art
With modern manufacturing techniques, the yield of digital CMOS or memory circuits is primarily limited by random defects that result from random effects such as dust particles or other materials floating in the air, a person coughing or sneezing, etc. Non-random (systematic) defects that result from problems with the manufacturing process and are reproduced regularly on successive ICs, as well as parametric defects in which a part may not quite meet specifications but is still functional, are reduced or eliminated through rapid learning techniques during the course of manufacturing products in large volumes. Several yield models have been developed to calculate defect limited yield as a function of die area and defect density; see Cheek and O'Donoghue, "Yield Modeling in a DFM Environment: A Bibliography", International Semiconductor Manufacturing Science Symposium, San Francisco, 1993.
The validity of such yield models is based upon several assumptions. First, it is assumed that the spatial defect distribution on the wafer surface is random or clustered random. Second, the parametric component of yield loss is assumed to be negligible. Third, the number of gross process induced defects on the wafer is assumed to be small. Finally, a significant portion of the circuitry is assumed to be highly dense, resulting in a relatively large critical area (that region of a circuit in which the presence of a defect will result in a catastrophic failure).
For analog or mixed analog/digital circuits, however, the above assumptions for random defect limited yield do not apply. These circuits typically have smaller critical areas than digital circuits, and are more sensitive to process parameter variations and systematic process induced defects. An identification of the root cause of yield loss on analog circuitry requires that the various mechanisms contributing to the effective defect density, such as random defects versus systematic defects and gross defects versus parametric defects, be distinguished from each other.
Yield models used for digital or memory yield prediction use two parameters: defect density and die or chip area. The defect density is a curve fitted parameter based upon the relationship between die area and measured yield. It is used to model all yield loss mechanisms. However, for mixed-signal or analog circuits, where all yield loss cannot be accounted for by a defect density, an additional parameter that represents systematic or non-random yield loss is necessary. The purpose of the analysis is to identify systematic yield loss components in real time and also to quantify a general Y.sub.o (non-random yield loss) parameter for use in yield models.
IC chips are fabricated as separate dice on semiconductor wafers. Each die is probed for testing, with failing dice marked with an ink spot. The passing dice are taken from the wafer and assembled into packaged parts, which are again tested. The patterns of good and failing chips at either a wafer or a packaged part level have been used to identify underlying problems in the manufacturing process. This has involved generating a two-dimensional wafer pattern map upon which the defective chips are noted, overlying the wafer defect maps on wafer "signature" maps which display typical defect patterns for various manufacturing line problems, and manually comparing the two in an effort to establish correlations. The identification of statistical trends and development of correlation models has also been used for fault diagnosis; see Kiberian and Strojwas, "Using Spatial Information To Analyze Correlations Between Test Structure Data", IEEE Transactions on Semiconductor Manufacturing, Vol. 4, No. 3, August 1991. However, the graphical analysis of two-dimensional wafer patterns is an interactive and time consuming process and not practical for application in a real time manufacturing flow.
Another technique that has been used to determine the systematic versus random components of yield loss involves "windowing" on a wafer map. This technique is described, for example, in Stapper et al., "Integrated Circuit Yield Statistics", Proceedings of the IEEE, Vol 71, No 4, April 1983. It allows the yield to be determined as a function of a "window" of increasing size that is moved around the wafer map. The window is increased from a single die size to two dice, three dice, four dice, and further multiples. Since the likelihood of a defect being included within a particular window area increases as the size of the window become greater, the yield experiences a corresponding reduction. The yields for different window sizes are plotted on the Y-axis of a logarithmic scale against the window area, which is plotted on the X-axis. The resulting curves are extended to intercept the Y-axis, at which the window size is a theoretical zero. The point at which the Y-axis is intercepted is referred to as Y.sub.o, and is taken to represent the portion of the total defects attributable to random defects. While this technique provides an approximation of the random versus non-random components of defects that effect wafer yield, it is laborious, time consuming and not particularly accurate.
A further limitation on the amount of useful information that can be obtained with present defect analysis procedures stems from the nature of IC testing. Numerous different tests, up to 100 in number, are typically performed on each die. The tests generally begin with those having strict pass requirements, and are progressively relaxed for later tests. The distribution of the pass/fail results for the various tests, or for combinations of the tests, is referred to as the "bin distribution". The analysis of bin data is useful for manufacturing process control and long term reliability; see Riordan and Vasques, "Statistical Bin Limits: Containing Factory Excursions Near the Source", 18th Annual Reliability Testing Institute, University of Arizona, May, 1992.
The pattern of results at each different test level in the bin or test distribution provides additional information for identifying desirable corrections to the manufacturing process. The bin distribution is also useful in recategorizing a specific die which satisfies some but not all of the various tests, and can be used for applications which have relaxed specifications. However, the additional test data available from the bin distribution multiplies the time required to perform the test analysis.